Re: [PATCH v3 07/13] clk: eyeq: Skip post-divisor when computing PLL frequency

[Stephen Boyd]

Quoting Benoît Monin (2026-02-26 05:33:51)
> The output of the PLL is routed before the post-divisor so it should be
> ignored when computing the frequency of the PLL, functional change is
> implemented to reflect how the clock signal is wired internally.
> 
> For the PLL of the EyeQ5, EyeQ6L, and EyeQ6H, this change has no impact
> as the post-divisor is either reported as disabled or set to 1. The PLL
> frequency is the same before and after the post-divisor.
> 
> For the PLL in EyeQ6Lplus, however, the post-divisor is not 1, so it must
> be ignored to compute the correct frequency.
> 
> Signed-off-by: Benoît Monin <benoit.monin@xxxxxxxxxxx>
> ---

Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>