RE: [PATCH v7 3/4] dt-bindings: iio: adc: ad4080: add AD4880 support

[Miclaus, Antoniu]

> -----Original Message-----
> From: Jonathan Cameron <jic23@xxxxxxxxxx>
> Sent: Saturday, March 21, 2026 2:08 PM
> To: Miclaus, Antoniu <Antoniu.Miclaus@xxxxxxxxxx>
> Cc: Lars-Peter Clausen <lars@xxxxxxxxxx>; Hennerich, Michael
> <Michael.Hennerich@xxxxxxxxxx>; David Lechner <dlechner@xxxxxxxxxxxx>;
> Sa, Nuno <Nuno.Sa@xxxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>; Krzysztof
> Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>;
> Olivier Moysan <olivier.moysan@xxxxxxxxxxx>; linux-iio@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v7 3/4] dt-bindings: iio: adc: ad4080: add AD4880
> support
> 
> [External]
> 
> On Sat, 21 Mar 2026 12:01:53 +0200
> Antoniu Miclaus <antoniu.miclaus@xxxxxxxxxx> wrote:
> 
> > Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC
> > with integrated fully differential amplifiers (FDA).
> >
> > The AD4880 has two independent ADC channels, each with its own SPI
> > configuration interface. This requires:
> > - Two entries in reg property for primary and secondary channel
> >   chip selects
> > - Two io-backends entries for the two data channels
> From the v6 discussion.  I'd just like to know a little more on this.
> Are they really separate backends?
> 
Yes, they are separate backends. The FPGA reference design
instantiates two independent axi_ad408x IP cores
The AD4880 is essentially two AD4080 dies in one package.

The two data streams are merged by a util_cpack2 channel
packer before reaching a single DMA:

    axi_ad408x (ch A) --
                         --> util_cpack2 --> single DMA
    axi_ad408x (ch B) --/

Each backend needs independent LVDS alignment and lane
configuration, so a single-backend-with-channel-parameter
model wouldn't fit here.

https://github.com/analogdevicesinc/hdl/blob/main/projects/ad4880_fmc_evb/common/ad4880_fmc_evb_bd.tcl

> Given discussion about interleaved data, I was kind of assuming they
> were different front end interfaces to a single backend IP.
> 
> The freedom this binding is giving is for those two backends to be
> completely unrelated. I'm not sure if we want that.
> 
> Jonathan
> 
> 
> >
> > Reviewed-by: David Lechner <dlechner@xxxxxxxxxxxx>
> > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@xxxxxxxxxx>
> > ---
> > Changes in v7:
> >   - No changes
> >
> >  .../bindings/iio/adc/adi,ad4080.yaml          | 53 ++++++++++++++++++-
> >  1 file changed, 51 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> > index ccd6a0ac1539..0cf86c6f9925 100644
> > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> > @@ -18,7 +18,11 @@ description: |
> >    service a wide variety of precision, wide bandwidth data acquisition
> >    applications.
> >
> > +  The AD4880 is a dual-channel variant with two independent ADC
> channels,
> > +  each with its own SPI configuration interface.
> > +
> >    https://www.analog.com/media/en/technical-documentation/data-
> sheets/ad4080.pdf
> > +  https://www.analog.com/media/en/technical-documentation/data-
> sheets/ad4880.pdf
> >
> >  $ref: /schemas/spi/spi-peripheral-props.yaml#
> >
> > @@ -31,9 +35,15 @@ properties:
> >        - adi,ad4084
> >        - adi,ad4086
> >        - adi,ad4087
> > +      - adi,ad4880
> >
> >    reg:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> > +    description:
> > +      SPI chip select(s). For single-channel devices, one chip select.
> > +      For multi-channel devices like AD4880, two chip selects are required
> > +      as each channel has its own SPI configuration interface.
> >
> >    spi-max-frequency:
> >      description: Configuration of the SPI bus.
> > @@ -57,7 +67,10 @@ properties:
> >    vrefin-supply: true
> >
> >    io-backends:
> > -    maxItems: 1
> > +    minItems: 1
> > +    items:
> > +      - description: Backend for channel A (primary)
> > +      - description: Backend for channel B (secondary)
> >
> >    adi,lvds-cnv-enable:
> >      description: Enable the LVDS signal type on the CNV pin. Default is CMOS.
> > @@ -78,6 +91,25 @@ required:
> >    - vdd33-supply
> >    - vrefin-supply
> >
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: adi,ad4880
> > +    then:
> > +      properties:
> > +        reg:
> > +          minItems: 2
> > +        io-backends:
> > +          minItems: 2
> > +    else:
> > +      properties:
> > +        reg:
> > +          maxItems: 1
> > +        io-backends:
> > +          maxItems: 1
> > +
> >  additionalProperties: false
> >
> >  examples:
> > @@ -98,4 +130,21 @@ examples:
> >            io-backends = <&iio_backend>;
> >          };
> >      };
> > +  - |
> > +    spi {
> > +        #address-cells = <1>;
> > +        #size-cells = <0>;
> > +
> > +        adc@0 {
> > +          compatible = "adi,ad4880";
> > +          reg = <0>, <1>;
> > +          spi-max-frequency = <10000000>;
> > +          vdd33-supply = <&vdd33>;
> > +          vddldo-supply = <&vddldo>;
> > +          vrefin-supply = <&vrefin>;
> > +          clocks = <&cnv>;
> > +          clock-names = "cnv";
> > +          io-backends = <&iio_backend_cha>, <&iio_backend_chb>;
> > +        };
> > +    };
> >  ...