[PATCH v6 1/3] hwmon: (pmbus) export pmbus_wait and pmbus_update_ts

[Pradhan, Sanman]

From: Sanman Pradhan <psanman@xxxxxxxxxxx>

Export pmbus_wait() and pmbus_update_ts() so that PMBus device
drivers which perform raw I2C transfers outside the core helpers
can keep the PMBus core delay bookkeeping in sync.

Move PMBUS_OP_WRITE and PMBUS_OP_PAGE_CHANGE from pmbus_core.c to
pmbus.h so device drivers can pass the correct operation type flags
to pmbus_update_ts().

This is needed by the max31785 driver, which performs raw
i2c_transfer() calls for its 4-byte extended fan speed reads that
cannot use the standard PMBus word read path.

Signed-off-by: Sanman Pradhan <psanman@xxxxxxxxxxx>
---
v6:
- No changes to this patch in this version.

v5:
- Removed spinlock usage; pmbus_wait() and pmbus_update_ts() now rely
  solely on update_lock serialization.

v4:
- No changes to logic; standardized on the Juniper email address to
  resolve the From/SOB mismatch.

v3:
- No changes to this patch in this version.

v2:
- New patch in the series.
- Export pmbus_wait() and pmbus_update_ts() to the PMBUS namespace.
- Relocate PMBUS_OP_* bitmasks to the subsystem header.
---
 drivers/hwmon/pmbus/pmbus.h      | 6 ++++++
 drivers/hwmon/pmbus/pmbus_core.c | 9 +++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/hwmon/pmbus/pmbus.h b/drivers/hwmon/pmbus/pmbus.h
index 3ddcb742d289e..deb556971a726 100644
--- a/drivers/hwmon/pmbus/pmbus.h
+++ b/drivers/hwmon/pmbus/pmbus.h
@@ -424,6 +424,10 @@ enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv, nvidia195mv };
 #define PMBUS_REV_12 0x22	/* PMBus revision 1.2 */
 #define PMBUS_REV_13 0x33	/* PMBus revision 1.3 */
 
+/* Operation type flags for pmbus_update_ts */
+#define PMBUS_OP_WRITE		BIT(0)
+#define PMBUS_OP_PAGE_CHANGE	BIT(1)
+
 struct pmbus_driver_info {
 	int pages;		/* Total number of pages */
 	u8 phases[PMBUS_PAGES];	/* Number of phases per page */
@@ -541,6 +545,8 @@ int pmbus_regulator_init_cb(struct regulator_dev *rdev,
 
 void pmbus_clear_cache(struct i2c_client *client);
 void pmbus_set_update(struct i2c_client *client, u8 reg, bool update);
+void pmbus_wait(struct i2c_client *client);
+void pmbus_update_ts(struct i2c_client *client, int op);
 int pmbus_set_page(struct i2c_client *client, int page, int phase);
 int pmbus_read_word_data(struct i2c_client *client, int page, int phase,
 			 u8 reg);
diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c
index 4d7634ee61484..ada962d9d2762 100644
--- a/drivers/hwmon/pmbus/pmbus_core.c
+++ b/drivers/hwmon/pmbus/pmbus_core.c
@@ -36,8 +36,7 @@
  * The type of operation used for picking the delay between
  * successive pmbus operations.
  */
-#define PMBUS_OP_WRITE		BIT(0)
-#define PMBUS_OP_PAGE_CHANGE	BIT(1)
+/* PMBUS_OP_WRITE and PMBUS_OP_PAGE_CHANGE are defined in pmbus.h */
 
 static int wp = -1;
 module_param(wp, int, 0444);
@@ -173,7 +172,7 @@ void pmbus_set_update(struct i2c_client *client, u8 reg, bool update)
 EXPORT_SYMBOL_NS_GPL(pmbus_set_update, "PMBUS");
 
 /* Some chips need a delay between accesses. */
-static void pmbus_wait(struct i2c_client *client)
+void pmbus_wait(struct i2c_client *client)
 {
 	struct pmbus_data *data = i2c_get_clientdata(client);
 	s64 delay = ktime_us_delta(data->next_access_backoff, ktime_get());
@@ -181,9 +180,10 @@ static void pmbus_wait(struct i2c_client *client)
 	if (delay > 0)
 		fsleep(delay);
 }
+EXPORT_SYMBOL_NS_GPL(pmbus_wait, "PMBUS");
 
 /* Sets the last operation timestamp for pmbus_wait */
-static void pmbus_update_ts(struct i2c_client *client, int op)
+void pmbus_update_ts(struct i2c_client *client, int op)
 {
 	struct pmbus_data *data = i2c_get_clientdata(client);
 	const struct pmbus_driver_info *info = data->info;
@@ -197,6 +197,7 @@ static void pmbus_update_ts(struct i2c_client *client, int op)
 	if (delay > 0)
 		data->next_access_backoff = ktime_add_us(ktime_get(), delay);
 }
+EXPORT_SYMBOL_NS_GPL(pmbus_update_ts, "PMBUS");
 
 int pmbus_set_page(struct i2c_client *client, int page, int phase)
 {
-- 
2.34.1