Re: [PATCH v1 2/2] i2c: imx: ensure no clock is generated after last read

[Andi Shyti]

Hi Carlos,

> > > > > > When reading from the I2DR register, right after releasing the
> > > > > > bus by clearing MSTA and MTX, the I2C controller might still
> > > > > > generate an additional clock cycle which can cause devices to
> > > > > > misbehave. Ensure to
> > > > >
> > > > > Do you means SCL have additional toggle? You capture waveform?
> > > > >
> > > >
> > > > Yes exactly. We were able to capture the waveform when the issue
> > > > happens. It doesn't always happen though, it depends on how much
> > > > time passes between clearing MSTA and MTX and reading from I2DR.
> > > >
> > > > If you want to see the waveform, I uploaded it to our server:
> > > > https://share.toradex.com/dwnhcrl6b9toib6
> > > > You can see the additional clock at the right end, after "0x17 + NAK".
> > >
> > > Have you had a chance to look at the waveform? Do you have any
> > > concerns about the proposed solution?
> > 
> > I am fine. Add carlos, who did many work about I2C.
> > 
> > Frank
> 
> Hi, 
> 
> Just review this series, looks this series patch make this fix for the limitation[1] safer:
> "It must generate STOP before read I2DR to prevent controller from generating another clock cycle".
> 
> Previous patch[2] has done this to avoid the limitation. However according to the waveform, I2C controller still generated an additional clock cycle sometime.
> 
> The key of patch is ensure to read the last bytes after the bus is not busy anymore to avoid this another clock cycle.So these patches are fine to me also.
> 
> [1] 054b62d9f25c ("i2c: imx: fix the i2c bus hang issue when do repeat restart")
> [2] 5f5c2d4579ca ("i2c: imx: prevent rescheduling in non dma mode")

Sorry, I'm not understanding your point here. Are you suggesting
to change the Fixes tag to [1]?

Thanks,
Andi