Re: [PATCH 2/2] clk: renesas: r9a09g057: Add PCIe clocks and reset

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, 12 Mar 2026 at 12:15, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add clocks and reset entries for the PCIe controller.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -508,6 +508,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(8, BIT(6))),
>         DEF_MOD("gbeth_1_aclk_i",               CLK_PLLDTY_DIV8, 12, 3, 6, 3,
>                                                 BUS_MSTOP(8, BIT(6))),
> +       DEF_MOD("pcie_0_aclk",                  CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
> +                                               BUS_MSTOP(1, BIT(13) | BIT(15))),
> +       DEF_MOD("pcie_0_clk_pmu",               CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
> +                                               BUS_MSTOP(1, BIT(13) | BIT(15))),

So the PCIE0 and PCIE1 modules are always stopped/started together, oh well...

>         DEF_MOD("cru_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
>                                                 BUS_MSTOP(9, BIT(4))),
>         DEF_MOD_NO_PM("cru_0_vclk",             CLK_PLLVDO_CRU0, 13, 3, 6, 19,

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds