[PATCH v1 1/3] misc: amd-sbi: Add revision support for AMD Venice platform

[Akshay Gupta]

The AMD Venice platform uses revision 0x31 and a two-byte register
address size. Add the revision to the CPUID and MCAMSR protocol
functions to ensure correct protocol identification.

Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@xxxxxxx>
Signed-off-by: Akshay Gupta <Akshay.Gupta@xxxxxxx>
---
 drivers/misc/amd-sbi/rmi-core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c
index c3a58912d6db..1d4933c69dd2 100644
--- a/drivers/misc/amd-sbi/rmi-core.c
+++ b/drivers/misc/amd-sbi/rmi-core.c
@@ -214,6 +214,7 @@ static int rmi_cpuid_read(struct sbrmi_data *data,
 			goto exit_unlock;
 		break;
 	case 0x21:
+	case 0x31:
 		ret = rmi_cpuid_input_ext(data, msg, thread);
 		if (ret)
 			goto exit_unlock;
@@ -327,6 +328,7 @@ static int rmi_mca_msr_read(struct sbrmi_data *data,
 			goto exit_unlock;
 		break;
 	case 0x21:
+	case 0x31:
 		ret = rmi_mcamsr_input_ext(data, msg, thread);
 		if (ret)
 			goto exit_unlock;
-- 
2.34.1