Re: [PATCH v3 2/3] arm64: dts: qcom: Introduce Eliza Soc base dtsi

[Konrad Dybcio]

On 3/18/26 11:19 AM, Abel Vesa wrote:
> Introduce the initial support for the Qualcomm Eliza SoC. It comes in
> different flavors. There is SM7750 for mobiles and then QC7790S/M for IoT.
> Describe the common parts under a common dtsi.
> 
> The initial submission enables support for:
> - CPU nodes with cpufreq and cpuidle support
> - Global Clock Controller (GCC)
> - Resource State Coordinator (RSC) with clock controller & genpd provider
> - Interrupt controller
> - Power Domain Controller (PDC)
> - Vendor specific SMMU
> - SPMI bus arbiter
> - Top Control and Status Register (TCSR)
> - Top Level Mode Multiplexer (TLMM)
> - Debug UART
> - Reserved memory nodes
> - Interconnect providers
> - System timer
> - UFS
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
> ---

[...]

> +		gcc: clock-controller@100000 {
> +			compatible = "qcom,eliza-gcc";
> +			reg = <0x0 0x00100000 0x0 0x1f4200>;
> +
> +			clocks = <&bi_tcxo_div2>,
> +				 <&sleep_clk>,
> +				 <0>,
> +				 <0>,
> +				 <&ufs_mem_phy 0>,
> +				 <&ufs_mem_phy 1>,
> +				 <&ufs_mem_phy 2>,
> +				 <0>;

power-domains = <&rpmhpd RPMHPD_CX>;

[...]

> +			clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> +				<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;

please align the '<'s

[...]

> +		ice: crypto@1d88000 {
> +			compatible = "qcom,eliza-inline-crypto-engine",
> +				     "qcom,inline-crypto-engine";
> +			reg = <0x0 0x01d88000 0x0 0x18000>;
> +
> +			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

I believe you will be affected by the change (?)

https://lore.kernel.org/all/20260318-precious-qualified-oryx-ef619f@quoll/

[...]

> +		spmi: arbiter@c400000 {
> +			compatible = "qcom,eliza-spmi-pmic-arb",
> +				     "qcom,x1e80100-spmi-pmic-arb";
> +			reg = <0 0x0c400000 0 0x3000>,
> +			      <0 0x0c500000 0 0x400000>,
> +			      <0 0x0c440000 0 0x80000>;
> +			reg-names = "core", "chnls", "obsrvr";

0x0, one a line please (also below)

Konrad