Re: [PATCH v3 2/2] arm64: dts: qcom: sm8250-asus-obiwan: Add ASUS ROG Phone 3
From: Konrad Dybcio
Date: Wed Mar 18 2026 - 06:28:45 EST
On 3/11/26 3:43 AM, Alexander Koskovich wrote:
> Supported functionality as of this initial submission:
> * Armor Case & Dock Hall Sensors
> * Camera flash/torch LED
> * Display (Tianma TA066VVHM03)
> * DisplayPort Alt Mode
> * Macro Camera (OV8856)
> * GPU (Adreno 650)
> * NFC (NXP PN553)
> * Power Button, Volume Keys
> * Regulators
> * Remoteprocs (ADSP, CDSP, SLPI)
> * UFS
> * USB
> * Video Codec (Venus)
> * Wi-Fi / Bluetooth (QCA6390)
>
> Signed-off-by: Alexander Koskovich <akoskovich@xxxxx>
> ---
[...]
> + /*
> + * There are also ER & EVB boards, but those have meaningful hardware
> + * differences that make them not compatible with this devicetree.
> + */
> + qcom,board-id = <31 0>, /* ER2 */
> + <40 0>, /* PR */
> + <41 0>, /* PR2 */
> + <50 0>; /* MP */
I would guesstimate MP is Mass Production and everything before that is
engineering samples.. perhaps that doesn't hurt - maybe some curious Asus
engineer swings by one day!
[...]
> +&i2c1 {
> + status = "okay";
Please ensure 'status' is the last property, preceded by a \n
> + clock-frequency = <400000>;
> +
> + nfc@28 {
> + compatible = "nxp,pn553",
> + "nxp,nxp-nci-i2c";
> + reg = <0x28>;
> +
> + interrupt-parent = <&tlmm>;
> + interrupts = <111 IRQ_TYPE_EDGE_RISING>;
interrupts-extended = <&tlmm 111 ...>
> +
> + enable-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
> + firmware-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-0 = <&nfc_en_default>,
> + <&nfc_clk_req_default>,
> + <&nfc_firmware_default>,
> + <&nfc_irq_default>;
You can bunch them up into:
nfc_default_state: xyz-abc-state {
nfc-en-pins {
pins = "....
...
};
nfc-clk-req-pins {
pins = "...
};
};
> + /*
> + * When low the USB 2 data lanes are routed to the bottom USB port.
> + * When high they are routed to the pogo port on the side of the device.
> + */
> + usb2_mux_en: usb2-mux-en-default-state {
> + pins = "gpio9";
> + function = PMIC_GPIO_FUNC_NORMAL;
> + power-source = <0>;
> + output-low;
> + };
[...]
> + source-pdos = <PDO_FIXED(5000, 900,
> + PDO_FIXED_DUAL_ROLE |
> + PDO_FIXED_USB_COMM |
> + PDO_FIXED_DATA_SWAP)>;
> +
> + sink-pdos = <PDO_FIXED(5000, 3000,
> + PDO_FIXED_DUAL_ROLE |
> + PDO_FIXED_USB_COMM |
> + PDO_FIXED_DATA_SWAP)
> + PDO_FIXED(9000, 3000, 0)
> + PDO_FIXED(12000, 2250, 0)>;
Both ports have the same PDOs - will this kaboom if you plug in two chargers?
[...]
> + wlan_en_default: wlan-default-state {
> + pins = "gpio20";
> + function = "gpio";
> + drive-strength = <16>;
> + output-low;
> + bias-pull-up;
> + };
> +
> + bt_en_default: bt-default-state {
> + pins = "gpio21";
> + function = "gpio";
> + drive-strength = <16>;
> + output-low;
> + bias-pull-up;
> + };
you can drop output-low from both - the PMU driver will set it via the
GPIO APIs
[...]
> +&usb_2 {
> + pinctrl-0 = <&rt1715_mux_en>, <&usb2_mux_en>;
> + pinctrl-names = "default";
> +
> + /*
> + * Disable USB3 clock requirement as the bottom port only supports USB2.
> + * The USB3 lanes are routed through the pogo connector on this board for
> + * use with accessories, so will need to revisit this when we start to add
> + * support for those.
> + */
> + qcom,select-utmi-as-pipe-clk;
So, is that right?
┌───────┐
│ POGO │
└──┬──┬─┘
superspeed │ │
┌─────────────────────────────┘ │
│ │
┌──────┼─┐ highspeed │
│ DWC3_2 ┼─────────────────────┐ ┌────┴──┐
└────────┘ └───┤ MUX ┼───────PM8150_GPIO9
┌─────────┐ └──┬────┘
│ GPIO170 │ │
└─────────┘ │
│ │
┌────────┐ RXTX ┌───┴──┐ ┌───┴──┐
│ UART ┼────────│ MUX ┼────────┤USB-C2│
└────────┘ └──┬───┘ └──────┘
│
▼
GND
Konrad