Re: [PATCH v2 1/2] x86/cpu: Disable CR pinning during CPU bringup

[Borislav Petkov]

On Tue, Mar 17, 2026 at 09:42:58AM +0530, Nikunj A. Dadhania wrote:
> 
> 
> On 3/17/2026 3:13 AM, Dave Hansen wrote: 
> > Either we change how alternatives patching works, we use some other
> > exception code, or we try and get CR4.FSGSBASE established as early as
> > possible on the secondaries.
> 
> Right, I moved FSGSBASE enablement to cpu_init_exception_handling() to 
> establish it early:
> 
> https://lore.kernel.org/all/1439b4f4-ff0c-4b6a-ac86-5c0da2d26cf5@xxxxxxx

So this thing does the following here.

CPU0 goes first, the APs follow.

I think that should be good as a stable fix, unless I'm missing something.

We can then do our rework ontop of unifying the CR4 init and pinning but that
will be future work which doesn't need stable anyway...

[    0.132839] cpu_init_exception_handling: CPU0: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU2, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU2: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU4, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU4: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU6, CR4: 0x3100f0
[    0.240204] cr4_init: CPU8, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU8: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU10, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU10: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU12, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU12: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU14, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU14: Set X86_CR4_FSGSBASE
[    0.240204] cpu_init_exception_handling: CPU6: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU1, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU1: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU3, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU3: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU5, CR4: 0x3100f0
[    0.240204] cr4_init: CPU7, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU7: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU9, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU9: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU11, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU11: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU13, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU13: Set X86_CR4_FSGSBASE
[    0.240204] cr4_init: CPU15, CR4: 0x3100f0
[    0.240204] cpu_init_exception_handling: CPU5: Set X86_CR4_FSGSBASE
[    0.240204] cpu_init_exception_handling: CPU15: Set X86_CR4_FSGSBASE

-- 
Regards/Gruss,
    Boris.

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