RE: [PATCH v5 13/20] drm: renesas: rz-du: mipi_dsi: Add support for RZ/G3E

[Biju Das]

Hi Tommaso,

Thanks for the patch.

> -----Original Message-----
> From: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> Sent: 13 February 2026 16:28
> Subject: [PATCH v5 13/20] drm: renesas: rz-du: mipi_dsi: Add support for RZ/G3E
> 
> Add MIPI DSI support for the Renesas RZ/G3E SoC.
> 
> RZ/V2H(P) and RZ/G3E share identical PLLDSI divider constraints from the DSI PHY perspective, so both
> can reuse the existing rzv2h_plldsi_div_limits structure. However, at the CPG level the limits
> differ:
> 
>  - PLLDSI0 limits apply when vclk1 is used.
>  - PLLDSI1 limits apply when vclk2 is used.
> 
> To support this introduce rzg3e_plldsis_limits for RZ/G3E SoC.
> 
> During rzv2h_dphy_mode_clk_check(), the appropriate limits are selected dynamically based on vclk_idx,
> which reflects the currently selected vclk.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>

Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Cheers,
Biju

> ---
> v4->v5:
>  - No changes.
> 
> v3->v4:
>  - No changes.
> 
> v2->v3:
>  - No changes.
> 
> v1->v2:
>  - No changes.
> 
>  .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c    | 33 ++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-
> du/rzg2l_mipi_dsi.c
> index 35de1a964dc0..27901dafab9a 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -590,7 +590,7 @@ static unsigned int rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi *dsi,
>  	mode_freq_hz = mul_u32_u32(mode_freq, KILO);
>  	mode_freq_millihz = mode_freq_hz * MILLI;
>  	parameters_found =
> -		rzv2h_get_pll_divs_pars(dsi->info->cpg_plldsi.limits[0],
> +		rzv2h_get_pll_divs_pars(dsi->info->cpg_plldsi.limits[dsi->vclk_idx],
>  					&cpg_dsi_parameters,
>  					dsi->info->cpg_plldsi.table,
>  					dsi->info->cpg_plldsi.table_size,
> @@ -1539,6 +1539,36 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev)
>  	pm_runtime_disable(&pdev->dev);
>  }
> 
> +RZG3E_CPG_PLL_DSI0_LIMITS(rzg3e_cpg_pll_dsi0_limits);
> +RZG3E_CPG_PLL_DSI1_LIMITS(rzg3e_cpg_pll_dsi1_limits);
> +
> +static const struct rzv2h_pll_limits *rzg3e_plldsis_limits[] = {
> +	&rzg3e_cpg_pll_dsi0_limits,
> +	&rzg3e_cpg_pll_dsi1_limits,
> +};
> +
> +static const u8 rzg3e_cpg_div_table[] = {
> +	2, 4, 6, 8, 10, 12, 14, 16,
> +};
> +
> +static struct rzg2l_mipi_dsi_hw_info rzg3e_mipi_dsi_info = {
> +	.dphy_init = rzv2h_mipi_dsi_dphy_init,
> +	.dphy_startup_late_init = rzv2h_mipi_dsi_dphy_startup_late_init,
> +	.dphy_exit = rzv2h_mipi_dsi_dphy_exit,
> +	.dphy_mode_clk_check = rzv2h_dphy_mode_clk_check,
> +	.dphy_conf_clks = rzv2h_dphy_conf_clks,
> +	.cpg_plldsi.limits = rzg3e_plldsis_limits,
> +	.cpg_plldsi.table = rzg3e_cpg_div_table,
> +	.cpg_plldsi.table_size = ARRAY_SIZE(rzg3e_cpg_div_table),
> +	.phy_reg_offset = 0x10000,
> +	.link_reg_offset = 0,
> +	.min_dclk = 5440,
> +	.max_dclk = 187500,
> +	.out_port = 2,
> +	.features = RZ_MIPI_DSI_FEATURE_16BPP |
> +		    RZ_MIPI_DSI_FEATURE_GPO0R,
> +};
> +
>  RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);
> 
>  static const struct rzv2h_pll_limits *rzv2h_plldsi_limits[] = { @@ -1577,6 +1607,7 @@ static const
> struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = {  };
> 
>  static const struct of_device_id rzg2l_mipi_dsi_of_table[] = {
> +	{ .compatible = "renesas,r9a09g047-mipi-dsi", .data =
> +&rzg3e_mipi_dsi_info, },
>  	{ .compatible = "renesas,r9a09g057-mipi-dsi", .data = &rzv2h_mipi_dsi_info, },
>  	{ .compatible = "renesas,rzg2l-mipi-dsi", .data = &rzg2l_mipi_dsi_info, },
>  	{ /* sentinel */ }
> --
> 2.43.0