Re: [PATCH spi-next 04/11] spi: spi-fsl-lpspi: fsl_lpspi_set_watermark(): use FIELD_PREP() to encode FIFO Status register

[Marc Kleine-Budde]

On 16.03.2026 18:16:01, Mark Brown wrote:
> On Mon, Mar 16, 2026 at 06:59:12PM +0100, Marc Kleine-Budde wrote:
> > On 16.03.2026 17:37:45, Mark Brown wrote:
> > > On Mon, Mar 16, 2026 at 05:49:48PM +0100, Marc Kleine-Budde wrote:
>
> > > > The param register's default value on the i.MX93 is:
>
> > > > | LPSPI1–LPSPI3:  0002_0303h
> > > > | LPSPI4:         0003_0303h
> > > > | LPSPI5–LPSPI8:  0002_0303h
>
> > > > This means a RX/TX-FIFO size of 1 << 3 == 8.
>
> > > Right, so the parsing code is using the wrong mask to extract the width
> > > here but with actual values it's fine.
>
> > No, the parsing code is correct, the width of the fields are 8 bits
> > (datasheet of all supported SoCs), but the values are "2" (i.MX7ulp,
> > S32G2) resp. "3" (i.MX93).
>
> Oh, dear, so that's potentially going to go badly if there's a SoC with
> a bigger FIFO that didn't also increase the watermark field width.  We
> should at least warn about that, and ideally do something sensible.

Good idea, I'll add a warning if the FIFO is bigger than the watermark
field.

To handle this situation I see 2 options:
- warning + limit the FIFO to the usable size due to the currently
  hard-coded watermark width - this will result in reduced throughput
- increase the watermark mask to 8 bits - which is basically how the
  unpatched driver works.
  As outlined in my previous mail, the other code in the driver takes
  care that the watermark stays within the limits.

> > into the watermark fields. So using the 3 bit mask in FIELD_PREP should
> > not be a problem, even on the IP cores with just 2 bit wide mask.
>
> Yeah, it's not broken right now - just landmines for potential future
> SoCs to trip over.

ACK

regards,
Marc

-- 
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