Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints

[Krzysztof Kozlowski]

On 16/03/2026 13:36, Swamil Jain wrote:
>>      description:
>>        Addresses to each DSS memory region described in the SoC's TRM.
>>      oneOf:
>>        - items:
>>            - description: common DSS register area
>>            - description: VIDL1 light video plane
>>            - description: VID video plane
>>            - description: OVR1 overlay manager for vp1
>>            - description: OVR2 overlay manager for vp2
>>            - description: VP1 video port 1
>>            - description: VP2 video port 2
>>            - description: common1 DSS register area
>>        - items:
>>            - description: common DSS register area
>>            - description: VIDL1 light video plane
>>            - description: OVR1 overlay manager for vp1
>>            - description: VP1 video port 1
>>            - description: common1 DSS register area
>>
>> .....(Similarly for reg-names, clocks, clock-names,...)
>>
>> allOf:
>>    - if:
>>        properties:
>>          compatible:
>>            contains:
>>              const: ti,am62l-dss
>>      then:
>>        properties:
>>          clock-names:
>>            maxItems: 2
>>          clocks:
>>            maxItems: 2
>>          reg:
>>            maxItems: 5
>>      else:
>>        properties:
>>          clock-names:
>>            minItems: 3
>>          clocks:
>>            minItems: 3
>>          reg:
>>            minItems: 8
>>
>> ```
>>
>> Could you please confirm on this?

If there is no common part of each list, then this looks correct. Other
way would be the example I wrote ~2 hours ago on DT IRC (different
patchset) - so the qcom,ufs way. It depends how readable is the final
schema.

> 
> Hi Krzysztof,
> 
> Gentle ping, could you please confirm on the above design?

If you do not hear from me or other reviewer for some time after asking
"shall I do like that", just send next version implementing what you
think should be done and mentioning in changelog, that this is how you
address reviewers feedback.

Best regards,
Krzysztof