Re: [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
From: Kathiravan Thirumoorthy
Date: Mon Mar 16 2026 - 05:10:58 EST
On 3/13/2026 6:18 PM, Konrad Dybcio wrote:
On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
Add initial device tree support for the Qualcomm IPQ5210 SoC andPlease define this in the SoC DTSI and enable it via a &uart1 {} reference
rdp504 board.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 93 +++++++++
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 304 ++++++++++++++++++++++++++++
3 files changed, 398 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..e7748af640cccffa5c83ec82c37aa441444c2b13 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -22,6 +22,7 @@ hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
new file mode 100644
index 0000000000000000000000000000000000000000..3d95939785bc5bd4f510e2f992f0a1e80848c8de
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "ipq5210.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ5210 RDP504";
+ compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ soc@0 {
+ qupv3: geniqup@1ac0000 {
+ status = "okay";
+
+ uart1: serial@1a84000 {
from the board DT
Ack.
[...]
+ xo: xo {"xo_board" is the convention in other DTs
Ack.
[...]
+ L2_0: l2-cache {labels must apparently be lowercase nowadays
Ack.
+ compatible = "cache";= <2>
+ cache-level = <0x2>;
Ack.
+ cache-unified;OP-TEE *and* SCM? What does the former do?
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scm {
+ compatible = "qcom,scm-ipq5210", "qcom,scm";
+ };
For OP-TEE, we have use cases like getting the random numbers, remoteproc PAS and few others.
For SCM, setting the download mode is one typical example where OP-TEE doesn't come into picture.
Please let me know if this helps.
[...]
+ soc@0 {should dma-ranges also be 36-bit?
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
Ack.
[...]
+ qupv3: geniqup@1ac0000 {I see there's only a single QUP wrapper - therefore I'm going to assume
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x01ac0000 0x0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
+ <&gcc GCC_QUPV3_AHB_SLV_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ status = "disabled";
there will never be a SoC where this needs to be disabled
Ack.
[...]
+Please uniformly keep a \n before status, file-wide
+ uart1: serial@1a84000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x01a84000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
Ack.
Konrad