[PATCH spi-next 11/11] spi: spi-fsl-lpspi: fsl_lpspi_set_bitrate(): don't treat devtype_data->prescale_max == 0 as a special case

[Marc Kleine-Budde]

The i.MX93 is affected by erratum ERR051608, the maximum prescaler value is
1 not 7 as in the original datasheet.

On unaffected SoC the maximum prescaler is 7. Commit 783bf5d09f86 ("spi:
spi-fsl-lpspi: limit PRESCALE bit in TCR register") added struct
fsl_lpspi_devtype_data to hold the system dependent prescale_max value.

Commit 9bbfb1ec959c ("spi: spi-fsl-lpspi: Treat prescale_max == 0 as no
erratum") introduced the special value 0 to signal the default and
corresponding run-time check with a conditional operator.

To simplify the code, set the prescale_max of imx7ulp_lpspi_devtype_data
and s32g_lpspi_devtype_data to 7 and in fsl_lpspi_set_bitrate() directly
use the fsl_lpspi->devtype_data->prescale_max.

On ARM64 this leads to a reduction of the code of 52 bytes:

| add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-52 (-52)
| Function                                     old     new   delta
| fsl_lpspi_setup_transfer.isra                956     936     -20
| $x                                          7144    7112     -32
| Total: Before=19675, After=19623, chg -0.26%

This partly reverts commit 9bbfb1ec959ce95f91cfab544f705e5257be3be1.

Cc: James Clark <james.clark@xxxxxxxxxx>
Signed-off-by: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>
---
 drivers/spi/spi-fsl-lpspi.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index 3a0e9726fa71..f2c7bb3bc4cc 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -96,7 +96,7 @@
 #define SR_CLEAR_MASK	GENMASK(13, 8)
 
 struct fsl_lpspi_devtype_data {
-	u8 prescale_max : 3; /* 0 == no limit */
+	u8 prescale_max : 3;
 	bool query_hw_for_num_cs : 1;
 };
 
@@ -143,8 +143,10 @@ struct fsl_lpspi_data {
 };
 
 /*
- * Devices with ERR051608 have a max TCR_PRESCALE value of 1, otherwise there is
- * no prescale limit: https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
+ * Devices with ERR051608 have a max TCR_PRESCALE value of 1, otherwise use
+ * the register limit of 7.
+ *
+ * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
  */
 static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
 	.prescale_max = 1,
@@ -152,10 +154,11 @@ static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
 };
 
 static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
-	/* All defaults */
+	.prescale_max = 7,
 };
 
 static const struct fsl_lpspi_devtype_data s32g_lpspi_devtype_data = {
+	.prescale_max = 7,
 	.query_hw_for_num_cs = true,
 };
 
@@ -348,7 +351,7 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 	int scldiv;
 
 	perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
-	prescale_max = fsl_lpspi->devtype_data->prescale_max ?: 7;
+	prescale_max = fsl_lpspi->devtype_data->prescale_max;
 
 	if (!config.speed_hz) {
 		dev_err(fsl_lpspi->dev,

-- 
2.51.0