Re: [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
From: Kathiravan Thirumoorthy
Date: Mon Mar 16 2026 - 03:19:17 EST
On 3/13/2026 6:54 PM, Krzysztof Kozlowski wrote:
On Wed, Mar 11, 2026 at 03:15:45PM +0530, Kathiravan Thirumoorthy wrote:
Add device tree bindings for IPQ5210 TLMM block.Drop |
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>
---
.../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 +++++++++++++++++++++
1 file changed, 141 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..3e5a46638385cf7925963c7e4b615c67e642152c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5210 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@xxxxxxxxxx>
+ - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>
+
+description: |
Ack.
Please do not combine completely independent series, targetting
different subsystems, into one patchset. It does not bring benefits but
only make everything trickier for maintainers which need to figure out
dependencies and cherry pick instead of applying entire series.
We raised this multiple times and it IS documented in your guideline, so
READ the internal docs.
Ack.
Ack.
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC....
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+unevaluatedProperties: falseDrop blank line
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5210-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ gpio-ranges = <&tlmm 0 0 54>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+
+ qup-uart1-default-state {
+ tx-pins {
+ pins = "gpio39";
+ function = "qup_se1_l2";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ rx-pins {
+ pins = "gpio38";
+ function = "qup_se1_l3";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+ };
+
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
Thanks!
Best regards,
Krzysztof