Re: [PATCH v2 6/8] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board and defconfig
From: Robin Murphy
Date: Wed Jul 02 2025 - 08:16:45 EST
On 2025-07-02 10:44 am, Albert Yang wrote:
[...]
diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
new file mode 100644
index 000000000000..ddff2cb82cb0
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "bst,c1200";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0x100>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0x200>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0x300>;
+ };
+
+ l2_cache: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ clk_mmc: clock-4000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ always-on;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
Your PPIs target 8 of the 4 CPUS? Either way you don't have GICv2,
please use the GICv3 binding.
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>;
+ interrupt-parent = <&gic>;
+
+ mmc0: mmc@22200000 {
+ compatible = "bst,c1200-dwcmshc-sdhci";
+ reg = <0x0 0x22200000 0x0 0x1000>,
+ <0x0 0x23006000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_mmc>;
+ clock-names = "core";
+ max-frequency = <200000000>;
+ bus-width = <8>;
+ non-removable;
+ dma-coherent;
Given the funky DMA setup, I can't help be mildly suspicious of this -
is the device genuinely I/O coherent and capable of snooping the CPU
caches, or are you only getting away with it because
dma_init_coherent_memory() happens to remap as non-cacheable regardless?
Thanks,
Robin.
+ status = "disabled";
+ };
+
+ uart0: serial@20008000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20008000 0x0 0x1000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@32800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ ranges;
+ reg = <0x0 0x32800000 0x0 0x10000>,
+ <0x0 0x32880000 0x0 0x100000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 897fc686e6a9..0a1cfaa19688 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_BLAIZE=y
+CONFIG_ARCH_BST=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y