Re: [PATCH v6 3/8] iio: accel: adxl313: add buffered FIFO watermark with interrupt handling

[David Lechner]

On 7/1/25 2:23 AM, Lothar Rubusch wrote:
> On Sat, Jun 28, 2025 at 7:16 PM Jonathan Cameron <jic23@xxxxxxxxxx> wrote:
>>
>> On Sun, 22 Jun 2025 12:29:32 +0000
>> Lothar Rubusch <l.rubusch@xxxxxxxxx> wrote:
>>
>>> Cover the following tasks:
>>> - Add scan_mask and scan_index to the IIO channel configuration. The
>>> scan_index sets up buffer usage. According to the datasheet, the ADXL313
>>> uses a 13-bit wide data field in full-resolution mode. Set the
>>> signedness, number of storage bits, and endianness accordingly.
>>>
>>> - Parse the devicetree for an optional interrupt line and configure the
>>> interrupt mapping based on its presence. If no interrupt line is
>>> specified, keep the FIFO in bypass mode as currently implemented.
>>>
>>> - Set up the interrupt handler. Add register access to detect and
>>> evaluate interrupts. Implement functions to clear status registers and
>>> reset the FIFO.
>>>
>>> - Implement FIFO watermark configuration and handling. Allow the
>>> watermark level to be set, evaluate the corresponding interrupt, read
>>> the FIFO contents, and push the data to the IIO channel.
>>>
>>> Signed-off-by: Lothar Rubusch <l.rubusch@xxxxxxxxx>
>> Hi Lothar,
>>
> 
> Hi Jonathan, there's still one thing about this patch [PATCH v6 3/8],
> I wanted to address:
> 
>         struct mutex    lock; /* lock to protect transf_buf */
> +       u8 watermark;
>         __le16          transf_buf __aligned(IIO_DMA_MINALIGN);
> +       __le16          fifo_buf[ADXL313_NUM_AXIS * ADXL313_FIFO_SIZE + 1];
>  };
> 
> Is this correct usage of the IIO_DMA_MINALIGN? My intention here is to
> have transf_buf and fifo_buf[...] aligned with the IIO_DMA_MINALIGN.
> 
> Sorry, I should have asked this earlier. I saw the sensor operating,
> but I'm unsure if perhaps DMA usage is setup correctly. Perhaps you
> could drop me a line of feedback here?
> 
> Best,
> L

Assuming that transf_bus and fifo_buf aren't used at the same time,
which seems unlikely, this looks correct.

As an example of what could be problematic would be if the driver
wrote to transf_buf while fifo_buf was being used for a SPI DMA
read. Then, when the DMA operation was done, it could write over
transf_buf with the old value from when the DMA operation started
because it was in the same memory cache line as fifo_buf.