[PATCH v1] dt-bindings: PCI: microchip,pcie-host: fix dma coherency property

[Conor Dooley]

From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
For some reason, instead of adding dma-noncoherent to the binding
the pointless, NOP, property dma-coherent was. Swap dma-coherent for
dma-noncoherent.

Fixes: 04aa999eb96fd ("dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent")
Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
---
CC: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
CC: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
CC: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
CC: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
CC: Rob Herring <robh@xxxxxxxxxx>
CC: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
CC: Conor Dooley <conor+dt@xxxxxxxxxx>
CC: linux-pci@xxxxxxxxxxxxxxx
CC: devicetree@xxxxxxxxxxxxxxx
CC: linux-kernel@xxxxxxxxxxxxxxx
---
 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 103574d18dbc2..56397df2a6eec 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -50,7 +50,7 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
-  dma-coherent: true
+  dma-noncoherent: true
 
   ranges:
     minItems: 1
-- 
2.45.2