On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote:
From: George Moussalem<george.moussalem@xxxxxxxxxxx>
Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5018 devices.
The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL.
The clock tree: .XO (48 MHZ)-->WiFi (multiplier/divider)--> 96 MHZ
to CMN PLL.