Re: [PATCH v2] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error

[Heiko Stübner]

Am Sonntag, 27. April 2025, 11:51:24 Mitteleuropäische Sommerzeit schrieb Algea Cao:
> When using HDMI PLL frequency division coefficient at 50.25MHz
> that is calculated by rk_hdptx_phy_clk_pll_calc(), it fails to
> get PHY LANE lock. Although the calculated values are within the
> allowable range of PHY PLL configuration.
> 
> In order to fix the PHY LANE lock error and provide the expected
> 50.25MHz output, manually compute the required PHY PLL frequency
> division coefficient and add it to ropll_tmds_cfg configuration
> table.
> 
> Signed-off-by: Algea Cao <algea.cao@xxxxxxxxxxxxxx>
> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>

Acked-by: Heiko Stuebner <heiko@xxxxxxxxx>