Re: [PATCH v6 2/5] dt-bindings: media: Add qcom,x1e80100-camss

[Bryan O'Donoghue]

On 24/04/2025 16:54, Krzysztof Kozlowski wrote:
> On 24/04/2025 12:17, Bryan O'Donoghue wrote:
> > On 24/04/2025 11:07, Krzysztof Kozlowski wrote:
> > > On 24/04/2025 11:34, Bryan O'Donoghue wrote:
> > > > On 24/04/2025 07:40, Krzysztof Kozlowski wrote:
> > > > > > +  vdd-csiphy-0p8-supply:
> > > > > Same comment as other series on the lists - this is wrong name. There
> > > > > are no pins named like this and all existing bindings use different name.
> > > >
> > > > The existing bindings are unfortunately not granular enough.
> > > >
> > > > I'll post s series to capture pin-names per the SoC pinout shortly.
> > > How are the pins/supplies actually called?
> > >
> > > Best regards,
> > > Krzysztof
> >
> > I don't think strictly algning to pin-names is what we want.
> >
> > Here are the input pins
> >
> > VDD_A_CSI_0_1_1P2
> > VDD_A_CSI_2_4_1P2
> > VDD_A_CSI_0_1_0P9
> > VDD_A_CSI_2_4_0P9
> >
> > I think the right way to represent this
> >
> > yaml:
> > csiphy0-1p2-supply
> > csiphy1-1p2-supply
>
> But there is no separate supply for csiphy0 and csiphy1. Such split
> feels fine if you have separate CSI phy device nodes, which now I wonder
> - where are they?
>
> Best regards,
> Krzysztof

The main hardware argument for it is probably these PHYs do live inside 
of the TITAN_TOP_GDSC power-domain, which is the same collapsible 
power-domain that all of the other CAMSS components live inside of.

As I recall we had a four way - albeit long discussion on this in 
Dublin, you, me, Vlad and Neil and my memory was we would implement 
multiple rails in the existing CAMSS PHY structure and then look at how 
to model the PHYs differently in DTS.

The Test Pattern Generators - TPGs would then also fit into this new 
model for the PHYs.

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bod